OLD Laboratory Session 3 - Sequential Logic

Objectives:

  • To study the fundamentals of basic sequential logic concepts and circuits
  • To become familiar with various types of latches and flip-flops.
  • To build and test a simple (4-bit) binary counter.

Equipment Required:

The equipment you require is as follows:

  • Your lab notebook
  • Your own lead kit (bought from the technicians' office).
  • CADET experimental unit.
  • Digital voltmeter (available at the workstations).
  • Collect hook-up wire and appropriate ICs from demonstrator. (You need to figure out which ICs you need, from those that are made available, and how many, for each specific experiment.)

Preparation:

There are several preparatory tasks that you must perform at the start of the lab session:

  1. Self-organise into groups of two at each workstation.
  2. Collect your individual logbooks from the demonstrator.
  3. On a new page in the logbook, fill in an appropriate heading for the lab session, e.g.:
    • Digital Electronics: Lab Session 3
    • Sequential Logic
    • Date: 28 Nov 2008
    • Partner Name: Ford Prefect
  4. Study the rest of the lab session instructions below, in full. You will need to do detailed background research and study in textbooks or online resources to properly understand these instructions.

Procedure:

The S-R Latch

  1. Connect the two NOR gates as shown in Figure 1.


    Figure 1: An S-R latch created using NOR gates

  2. Vary the inputs R and S (i.e. 0 and +5V). Attempt to obtain all the possible combinations for Q and/Q. Summarise the behaviour of the circuit in your logbook.

  3. In your opinion why is there a both a Q and /Q output from this circuit? In your opinion why does this circuit behave in the way it does?

The Gated (Clocked) S-R Latch


Figure 2: The Gated (Clocked) S-R Latch

The "gated" or "clocked" S-R latch behaves in a way that is synchronised with some kind of regular "clock" signal. The clock signal simply alternates regularly between high and low levels. Note that, in the practical experiments that follow, you should generate any required "clock" signals using the debounced momentary action push-button switches on the left side of the CADET unit (rather than the array of eight sliding switches at the bottom of the unit, which are not de-bounced).


Figure 3: A typical clock signal

  1. Copy the table below into your logbook. This is designed to show, for each possible combination of input signals (R and S) and current state (Qn and /Qn, or state at clock pulse n), what the state will be after the next clock pulse (Qn+1 and /Qn+1, or state at clock pulse n+1). Fill in the predicted values for Qn+1 and /Qn+1 in each possible case before attempting any experiment. Now construct the circuit in Figure 3. Measure the actual values for Qn+1 and /Qn+1 in each possible case, and fill them into the table. You can manually generate a single clock pulse by switching the clock signal from low to high and back again to low. (Note that you will have think a little bit about how you can systematically create the conditions corresponding to each row of the table.) Comment on whether the actual behaviour matches your predictions. Summarise the actual behaviour in words.

    PredictedActual
    Qn/QnRSQn+1/Qn+1Qn+1/Qn+1
    0100
    1000
    0101
    1001
    0110
    1010
    0111
    1011

  2. Figure 4 shows a D-type gated (clocked) latch. In your logbook, draw up a truth table for this D-type latch, based on the table shown above for the S-R latch (but modified as appropriate). Include columns for predicted and actual behavior. Fill in the predicted values before doing any experiments. Now convert your S-R latch into a D-type latch. Measure the actual behaviour in each possible case, and fill in the table accordingly. Comment on whether the actual behaviour matches your predictions. Summarise the actual behaviour in words.


    Figure 4: The D-type latch

The J-K Flip-Flop


Figure 5: The J-K flip-flop

Draw up a suitable truth table, including columns for both predicted and actual states, to record the behaviour of a J-K flip-flop. Fill in the predicted values before doing any experiments.

Using a 7473 Dual Master-Slave J-K Flip-Flop IC, set up a single J-K flip-flop. Measure the actualbehaviour in each possible case, and fill in the table accordingly. Comment on whether the actual behaviour matches your predictions. Summarise the actual behaviour in words.

A 4-Bit Binary Counter

Design, build, and test a 4-bit counter using J-K flip-flops. Document your design and experiments in your logbook. State clearly whether, on the basis of your experiments, you consider that your design worked correctly.

Conclusions:

  1. State briefly, but clearly, what you have learned from this session.
  2. How did you split the work between yourself and your partner?
  3. What was the most difficult aspect of the lab?
  4. State one thing you enjoyed about the session.
  5. State one thing you disliked about the session.
  6. Add any final comment of your own.


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