Preparation:
There are several preparatory tasks that you must perform at the start of the lab session:
- Self-organise into groups of two at each workstation.
- Collect your individual logbooks from the demonstrator.
- On a new page in the logbook, fill in an appropriate heading for the lab session, e.g.:
- Digital Electronics: Lab Session 3
- Sequential Logic
- Date: 28 Nov 2008
- Partner Name: Ford Prefect
- Study the rest of the lab session instructions below, in full. You will need to do detailed background research and study in textbooks or online resources to properly understand these instructions.
Procedure:
The S-R
Latch
Connect the two NOR gates as shown in Figure 1.
Figure 1: An
S-R
latch created using NOR gatesVary the inputs
R
andS
(i.e. 0 and +5V). Attempt to obtain all the possible combinations forQ
and/Q
. Summarise the behaviour of the circuit in your logbook.In your opinion why is there a both a
Q
and/Q
output from this circuit? In your opinion why does this circuit behave in the way it does?
Figure 3: A typical clock signal
Copy the table below into your logbook. This is designed to show, for each possible combination of input signals (
R
andS
) and current state (Qn
and/Qn
, or state at clock pulse n), what the state will be after the next clock pulse (Qn+1
and/Qn+1
, or state at clock pulse n+1). Fill in the predicted values forQn+1
and/Qn+1
in each possible case before attempting any experiment. Now construct the circuit in Figure 3. Measure the actual values forQn+1
and/Qn+1
in each possible case, and fill them into the table. You can manually generate a single clock pulse by switching the clock signal from low to high and back again to low. (Note that you will have think a little bit about how you can systematically create the conditions corresponding to each row of the table.) Comment on whether the actual behaviour matches your predictions. Summarise the actual behaviour in words.Predicted Actual Qn
/Qn
R
S
Qn+1
/Qn+1
Qn+1
/Qn+1
0
1
0
0
1
0
0
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
1
0
0
1
1
1
1
0
1
1
Figure 4 shows a
D
-type gated (clocked) latch. In your logbook, draw up a truth table for thisD
-type latch, based on the table shown above for theS-R
latch (but modified as appropriate). Include columns for predicted and actual behavior. Fill in the predicted values before doing any experiments. Now convert yourS-R
latch into aD
-type latch. Measure the actual behaviour in each possible case, and fill in the table accordingly. Comment on whether the actual behaviour matches your predictions. Summarise the actual behaviour in words.Figure 4: The
D
-type latch
The J-K
Flip-Flop
Figure 5: The J-K
flip-flop
Draw up a suitable truth table, including columns for both predicted and actual states, to record the behaviour of a J-K
flip-flop. Fill in the predicted values before doing any experiments.
Using a 7473 Dual Master-Slave J-K Flip-Flop IC, set up a single J-K
flip-flop. Measure the actualbehaviour in each possible case, and fill in the table accordingly. Comment on whether the actual behaviour matches your predictions. Summarise the actual behaviour in words.
A 4-Bit Binary Counter
Design, build, and test a 4-bit counter using J-K
flip-flops. Document your design and experiments in your logbook. State clearly whether, on the basis of your experiments, you consider that your design worked correctly.
Conclusions:
- State briefly, but clearly, what you have learned from this session.
- How did you split the work between yourself and your partner?
- What was the most difficult aspect of the lab?
- State one thing you enjoyed about the session.
- State one thing you disliked about the session.
- Add any final comment of your own.